The individual status registers are used to report different classes of instrument states or errors. The following status registers belong to the general model described in IEEE 488.2:
The STatus Byte (STB) gives a rough overview of the instrument status.
The IST flag combines the entire status information into a single bit that can be queried in a parallel poll.
The Event Status Register (ESR) indicates general instrument states.
The status registers below belong to the device-dependent SCPI register model:
The STATus:OPERation register contains conditions which are part of the instrument's normal operation.
The STATus:QUEStionable register indicates whether the data currently being acquired is of questionable quality.
The STATus:QUEStionable:LIMit<1|2> register indicates the result of the limit check.
The STatus Byte (STB) provides a rough overview of the instrument status by collecting the pieces of information of the lower registers. The STB represents the highest level within the SCPI hierarchy. A special feature is that bit 6 acts as the summary bit of the remaining bits of the status byte.
The STatus Byte (STB) is linked to the Service Request Enable (SRE) register on a bit-by-bit basis.
The STB corresponds to the CONDition part of an SCPI register, indicating the current instrument state.
The SRE corresponds to the ENABle part of an SCPI register.If a bit is set in the SRE and the associated bit in the STB changes from 0 to 1, a Service Request (SRQ) is generated on the GPIB bus.
Bit 6 of the SRE is ignored, because it corresponds to the summary bit of the STB.
The STB is read out using the command *STB? or a serial poll.
The SRE can be set using command *SRE and read using *SRE?.
The bits in the STB are defined as follows:
|
Bit No. |
Meaning |
|
3 |
QUEStionable status summary bit This bit is set if an EVENt bit is set in the QUEStionable register and the associated ENABle bit is set to 1. The bit indicates a questionable instrument status, which can be further pinned down by polling the QUEStionable register. |
|
5 |
ESB bit Sum bit of the event status register. It is set if one of the bits in the event status register is set and enabled in the event status enable register. Setting of this bit implies an error or an event which can be further pinned down by polling the event status register. |
In analogy to the Service Request (SRQ), the IST flag combines the entire status information in a single bit. It can be queried by means of a parallel poll.
The Parallel Poll Enable (PPE) register determines which bits of the STB contribute to the IST flag. The bits of the STB are ANDed with the corresponding bits of the PPE, with bit 6 being used as well in contrast to the SRE. The IST flag results from the ORing of all results.
The IST flag is queried using the command *IST?.
The Event Status Register (ESR) indicates general instrument states. It is linked to the Event Status Enable (ESE) register on a bit-by-bit basis.
The ESR corresponds to the CONDition part of an SCPI register, indicating the current instrument state.
The ESE corresponds to the ENABle part of an SCPI register. If a bit is set in the ESE and the associated bit in the ESR changes from 0 to 1, the ESB bit in the STatus Byte is set.
The Event Status Register (ESR) can be queried using ESR?.
The Event Status Enable (ESE) register can be set using the command *ESE and read using *ESE?.
The bits in the ESR are defined as follows:
|
Bit No. |
Meaning |
|
0 |
Operation Complete This bit is set on receipt of the command *OPC after all previous commands have been executed. |
The STATus:OPERation register contains conditions which are part of the instrument's normal operation.
The analyzer does not use the STATus:OPERation register:
The STATus:QUEStionable register indicates whether the data currently being acquired is of questionable quality. It can be queried using the commands STATus:QUEStionable:CONDition? or STATus:QUEStionable[:EVENt]?
The bits in the STATus:QUEStionable register are defined as follows:
|
Bit No. |
Meaning |
|
10 |
Limit Register summary This bit is set if a bit is set in the STATus:QUEStionable:LIMit1 register and the associated ENABle bit is set to 1. |
The STATus:QUEStionable:LIMit<1|2> registers indicate the result of the limit check. They can be queried using the commands STATus:QUEStionable:LIMit<1|2>:CONDition? or STATus:QUEStionable:LIMit<1|2>[:EVENt]? STATus:QUEStionable:LIMit1 is also the summary register of the lower-level STATus:QUEStionable:LIMit2 register.
The bits in the STATus:QUEStionable:LIMit1 register are defined as follows:
|
Bit No. |
Meaning |
|
0 |
LIMit2 Register summary This bit is set if a bit is set in the STATus:QUEStionable:LIMit2 register and the associated ENABle bit is set to 1. |
|
1 |
Failed Limit Check for Trace no. 1 This bit is set if any point on trace no. 1 fails the limit check. |
|
... |
... |
|
14 |
Failed Limit Check for Trace no. 14 This bit is set if any point on trace no. 14 fails the limit check. |
The bits in the STATus:QUEStionable:LIMit2 register are defined as follows:
|
Bit No. |
Meaning |
|
0 |
Not used |
|
1 |
Failed Limit Check for Trace no. 15 This bit is set if any point on trace no. 15 fails the limit check. |
|
2 |
Failed Limit Check for Trace no. 16 This bit is set if any point on trace no. 16 fails the limit check. |
The traces numbers 1 to 16 are assigned as follows:
Traces assigned to channels with smaller channel numbers have smaller trace numbers.
Within a channel, the order of traces reflects their creation time: The oldest trace has the smallest, the newest trace has the largest trace number. This is equivalent to the order of traces in the response string of the CALCulate<Ch>:PARameter:CATalog? query.
The number of traces monitored cannot exceed 16. If a setup contains more traces, the newest traces are not monitored.
